1. Field of the Invention
The present invention relates to semiconductor design, timing verification, and modeling, and Intellectual Property (IP) modeling using computer-aided design (CAD), and more particularly, to a black box timing method and a computer system for a very large scale integrated circuit (VLSI) design.
2. Description of the Related Art
Timing models for latch-based designs include gray box models, which are the best-known models, and models using transparent latch path collapsing techniques.
Such conventional timing models have problems in that internal components of the latch-based designs represented by the timing models should be re-verified during upper-level verification together with other designs. Accordingly, the conventional timing models are not suitable as timing models for Intellectual Property (IP). In particular, since the best-known gray box models retain delay information between all internal synchronous elements, the gray box models are large in size, thereby resulting in more complicated verification.
FIG. 1 illustrates a conventional black box timing model. Referring to FIG. 1, the conventional black box timing model includes a combination delay arc between an input and an output, a clock-to-output delay arc and a setup/hold arc extracted from synchronous elements and pins at the boundary of a macro block, and timing information on a pin at the boundary of a block which is a setup/hold time.
In order to obtain timing information on a circuit, a black box timing model made by Synopsis Inc. extracts a setup/hold arc only from a synchronous element adjacent to an input and extracts a clock-to-output delay arc from a synchronous element adjacent to an output. As for a flip-flop system, when single stage timing constraints of all flip flop pairs which are adjacent each other are met, the timing verification of the overall flip-flop system is completed. Accordingly, once synchronous elements adjacent to an input and an output in the flip-flop system satisfy timing conditions, other internal flip-flops automatically satisfy timing conditions.
However, a latch-synchronized system has a timing borrowing property. Accordingly, although latches adjacent to an input and an output satisfy timing conditions and thus there is no timing error, a timing error may occur in internal latches if a latch adjacent to an input borrows time from a fan-out latch and continuous time borrowing occurs. Also, the latch-synchronized system can be configured such that an output departure time is in linear proportion to an input arrival time, thereby making it difficult to model timing features.
Therefore, there is a pressing need for timing models that can be efficiently used for latch-based designs without re-verifying internal components of latch-based designs during upper-level verification. Also, there is a pressing need for a method of accurately modeling the characteristics of a latch-synchronized system having a timing borrowing property due to its transparency.